Designing and fabricating IC devices typically involves many steps, sometimes referred to as the “design flow.” The particular steps of a design flow often are dependent upon the type of the circuit, its complexity, the design team, and the circuit fabricator or foundry that will manufacture the circuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators. These steps aid in the discovery of errors in the design, and allow the designers and engineers to correct or otherwise improve the design.
Several steps are common to most design flows. Initially, the specification for a new circuit is transformed into a logical design, such as a register transfer level (RTL) description of the circuit. The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.” After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. The relationships between the electronic devices are then analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “formal verification.” Additionally, preliminary timing estimates for portions of the circuit are often made at this stage, using an assumed characteristic speed for each device, and incorporated into the verification process.
Once the components and their interconnections are established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various layers of material to manufacture the circuit. Typically, a designer will select groups of geometric elements representing IC components (e.g., contacts, channels, gates, etc.) and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Lines, also represented by geometric elements, are then routed between the geometric elements for IC components, forming the wiring used to interconnect the electronic devices. Circuit layout descriptions can be provided in many different formats. Once the design is finalized, the layout portion of the design can be used by fabrication tools to manufacture the circuit using a photolithographic process.
As designers and manufacturers continue to increase the number of circuit components in a given area and/or shrink the size of circuit components, the shapes reproduced on the substrate (and thus the shapes in the mask) become smaller and are placed closer together. This reduction in feature size increases the difficulty of faithfully reproducing the image intended by the design layout onto the substrate. Certain geometric shapes cannot be successfully manufactured in a particular manufacturing process. Historically, a chip manufacturer would have a failure analysis (FA) team identify these configurations, generate a geometric representation of the problematic features in those configurations, and then derive an engineering specification for excluding those problematic features from new designs. This type of engineering specification typically would be interpreted and formulated as a design rule. The derived design rule would then be added to the rule decks for use during a physical verification process.
Such a design rule checking (DRC) process works well when most problem features could be defined with simple one-dimensional checks (length, width, distance, etc.). More complex shapes, however, cannot be accurately described with existing scripting languages, inevitably resulting in checking errors. Moreover, significant time and expertise must be spent in the attempt to reach congruence between the original intent of the design rule and its implementation in a DRC process. Furthermore, as advanced nodes are being implemented, problematic configurations or patterns are now being identified by designers using lithography and optical process simulations well before silicon production and the creation of design rules. These designers also need the ability to capture and transfer problematic configurations to other designers.
To address the above challenges, pattern-aware physical verification techniques have been developed. These techniques are based more on original visual representation of a configuration and less on the abstraction and derivation. As a result, the process of defining a problematic configuration (pattern) in a layout design is dramatically simplified. Where pattern libraries have been established, pattern matching can be easily implemented into the layout verification flow for new designs, augmenting traditional design rule checking (DRC) and enabling designers to find and resolve more design issues earlier in the process flow. Patterns can also be used to implement optimum design configurations, improving design flow efficiency while ensuring manufacturability. Desirable or proven patterns can be implemented by designers with confidence that they will pass verification. Not only are design patterns an easier way to express complex 2-D and 3-D relationships, but they provide a directly useful way for design and manufacturing engineers to communicate design for manufacturing issues.
Pattern matching techniques have also been applied in the test and diagnosis area recently. Chip testing and failure diagnosis plays an important role in improving the yield of an IC design. Achieving high and stable yields helps ensure that the product is profitable and meets quality and reliability objectives. When a new manufacturing process is introduced, or a new product is introduced on a mature manufacturing process, yields will tend to be significantly lower than acceptable. The ability to meet profitability and quality objectives, and perhaps more importantly, time to market and time to volume objectives depend greatly on the rate at which these low yields can be ramped up.
Traditionally, logic-based scan test diagnosis, a software-based technique, uses structural test patterns and the design description to identify defect suspects. Physical failure analysis is then performed to locate defects and to identify the root-cause of failure. There is, however, a gap between what a traditional logic-based diagnosis tool can deliver and what failure analysis and yield engineers need. This is mainly because typically more than one physical location can explain the defective logical behavior observed in the failing cycles and each suspect location will often have multiple possible root causes associated with it. Fortunately, many systematic failures are caused by specific layout patterns. Matching traditional diagnosis results with layout patterns can thus improve the accuracy and resolution of a diagnosis tool, bridge the gap and speed up the yield ramp process. This type of approach is often referred to as pattern-aware (or layout-aware) diagnosis/yield analysis.
In both of the pattern-aware physical verification and pattern-aware failure diagnosis/yield analysis areas, it is desirable to group layout patterns together if they are identical, rotation variants, mirror variants, translation variants and/or scale variants. One reason is that these variants represent the same layout features that may be difficult to fabricate on a chip and/or prone to be defective on a fabricated chip. Another reason is that the grouping can reduce the storage requirement and computation costs for various simulation and analysis tools.